1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an SRAM cell and a method for fabricating the same, which can reduce a cell size.
2. Background of the Related Art
In general, the SRAM (Static Random Access Memory) cell is provided with a flipflop circuit having two access transistors, two drive transistors, and two load transistors. FIG. 1 illustrates an equivalent circuit of a COMS type SRAM cell.
Referring to FIG. 1, the COMS type SRAM cell has first, and second access transistors Q1 and Q2, first and second driver transistors Q3 and Q4, and first, and second load transistors Q5 and Q6.
That is, the SRAM cell is provided with first, and second inverters connected between a power source terminal and a ground terminal in parallel each having a PMOS transistor Q5 or Q6, and an NMOS transistor Q3 or Q4, and a first access transistor Q1 and a second access transistor Q2 each having a source (or a drain) connected to output terminals of the first, and second inverters.
A drain (or source) of the first access transistor Q1 and a drain (or source) of the second access transistor Q2 are connected to a first bitline BL and a second bitline /BL, respectively. Moreover, an input terminal of the first inverter is connected to an output terminal of the second inverter, and an input terminal of the second inverter is connected to an output terminal of the first inverter, to form a latch circuit.
A related art CMOS type SRAM cell will be explained, with reference to the attached drawings. FIG. 2 illustrates a layout of a related art CMOS type SRAM cell, FIG. 3 illustrates a section across a line III—III in FIG. 2, and FIG. 4 illustrates a section across a line II—II in FIG. 2.
Referring to FIGS. 2˜4, there is a device isolating film 12 formed in a field region of a semiconductor substrate 11 having the field region and an active region defined thereon, and an n-well region 13 and a p-well region 14 are formed in a surface of the semiconductor substrate 11.
There is a gate electrode 16 formed in an active region over the semiconductor substrate 11 with a gate insulating film 15 inbetween, and there are insulating sidewalls 17 at both sides of the gate electrode 16.
There are source/drain regions 18 in a surface of the semiconductor substrate 11 on both sides of the gate electrode 16, and a metal silicide film 19 on surfaces of the gate electrode 16 and the semiconductor substrate 11 having the source/drain regions 18 formed therein.
There are contact holes so as to expose parts of surfaces of the source/drain regions 18 and the gate electrode 16, and a nitride film 20, a BPSG film 21, and a PE-TEOS film 22 stacked in succession.
There is a tungsten plug 24 inside of the contact hole with a barrier metal film 23 disposed inbetween, and metal interconnections 25 on the tungsten plug 24 and a PE-TEOS film 22 adjacent thereto.
The metal interconnection 25 has a thickness of approx. 5000 Å for local interconnection of a Vcc line, a Vss line, impurity regions of transistors, and the gate electrode.
Thus, since the thickness of the metal interconnection in the related art SRAM cell is greater than 5000 Å, a distance A between the n-well region 13 and the p-well region 14 is 0.70 μm (0.40/0.30), and the local metal interconnection 25 has a pitch B of 0.45 μm (L/S=0.22/0.23), to form an area of approx. 4.60 μm2 in overall.
However, the related art SRAM cell has the following problems.
That is, because an area of the SRAM cell with 6-transistors has 4.60 μm2 when a 0.18 μm technology is employed owing to the local metal interconnection and Vcc/Vss lines each having greater than 5000 Å thickness, there has been a limit in reducing a cell size.